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Cypress Semiconductor /psoc63 /SAR /MUX_SWITCH0

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Interpret as MUX_SWITCH0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MUX_FW_P0_VPLUS)MUX_FW_P0_VPLUS 0 (MUX_FW_P1_VPLUS)MUX_FW_P1_VPLUS 0 (MUX_FW_P2_VPLUS)MUX_FW_P2_VPLUS 0 (MUX_FW_P3_VPLUS)MUX_FW_P3_VPLUS 0 (MUX_FW_P4_VPLUS)MUX_FW_P4_VPLUS 0 (MUX_FW_P5_VPLUS)MUX_FW_P5_VPLUS 0 (MUX_FW_P6_VPLUS)MUX_FW_P6_VPLUS 0 (MUX_FW_P7_VPLUS)MUX_FW_P7_VPLUS 0 (MUX_FW_P0_VMINUS)MUX_FW_P0_VMINUS 0 (MUX_FW_P1_VMINUS)MUX_FW_P1_VMINUS 0 (MUX_FW_P2_VMINUS)MUX_FW_P2_VMINUS 0 (MUX_FW_P3_VMINUS)MUX_FW_P3_VMINUS 0 (MUX_FW_P4_VMINUS)MUX_FW_P4_VMINUS 0 (MUX_FW_P5_VMINUS)MUX_FW_P5_VMINUS 0 (MUX_FW_P6_VMINUS)MUX_FW_P6_VMINUS 0 (MUX_FW_P7_VMINUS)MUX_FW_P7_VMINUS 0 (MUX_FW_VSSA_VMINUS)MUX_FW_VSSA_VMINUS 0 (MUX_FW_TEMP_VPLUS)MUX_FW_TEMP_VPLUS 0 (MUX_FW_AMUXBUSA_VPLUS)MUX_FW_AMUXBUSA_VPLUS 0 (MUX_FW_AMUXBUSB_VPLUS)MUX_FW_AMUXBUSB_VPLUS 0 (MUX_FW_AMUXBUSA_VMINUS)MUX_FW_AMUXBUSA_VMINUS 0 (MUX_FW_AMUXBUSB_VMINUS)MUX_FW_AMUXBUSB_VMINUS 0 (MUX_FW_SARBUS0_VPLUS)MUX_FW_SARBUS0_VPLUS 0 (MUX_FW_SARBUS1_VPLUS)MUX_FW_SARBUS1_VPLUS 0 (MUX_FW_SARBUS0_VMINUS)MUX_FW_SARBUS0_VMINUS 0 (MUX_FW_SARBUS1_VMINUS)MUX_FW_SARBUS1_VMINUS 0 (MUX_FW_P4_COREIO0)MUX_FW_P4_COREIO0 0 (MUX_FW_P5_COREIO1)MUX_FW_P5_COREIO1 0 (MUX_FW_P6_COREIO2)MUX_FW_P6_COREIO2 0 (MUX_FW_P7_COREIO3)MUX_FW_P7_COREIO3

Description

SARMUX Firmware switch controls

Fields

MUX_FW_P0_VPLUS

Firmware control: 0=open, 1=close switch between pin P0 and vplus signal. Write with ‘1’ to set bit.
MUX_FW_P1_VPLUS

Firmware control: 0=open, 1=close switch between pin P1 and vplus signal. Write with ‘1’ to set bit.
MUX_FW_P2_VPLUS

Firmware control: 0=open, 1=close switch between pin P2 and vplus signal. Write with ‘1’ to set bit.
MUX_FW_P3_VPLUS

Firmware control: 0=open, 1=close switch between pin P3 and vplus signal. Write with ‘1’ to set bit.
MUX_FW_P4_VPLUS

Firmware control: 0=open, 1=close switch between pin P4 and vplus signal. Write with ‘1’ to set bit.
MUX_FW_P5_VPLUS

Firmware control: 0=open, 1=close switch between pin P5 and vplus signal. Write with ‘1’ to set bit.
MUX_FW_P6_VPLUS

Firmware control: 0=open, 1=close switch between pin P6 and vplus signal. Write with ‘1’ to set bit.
MUX_FW_P7_VPLUS

Firmware control: 0=open, 1=close switch between pin P7 and vplus signal. Write with ‘1’ to set bit.
MUX_FW_P0_VMINUS

Firmware control: 0=open, 1=close switch between pin P0 and vminus signal. Write with ‘1’ to set bit.
MUX_FW_P1_VMINUS

Firmware control: 0=open, 1=close switch between pin P1 and vminus signal. Write with ‘1’ to set bit.
MUX_FW_P2_VMINUS

Firmware control: 0=open, 1=close switch between pin P2 and vminus signal. Write with ‘1’ to set bit.
MUX_FW_P3_VMINUS

Firmware control: 0=open, 1=close switch between pin P3 and vminus signal. Write with ‘1’ to set bit.
MUX_FW_P4_VMINUS

Firmware control: 0=open, 1=close switch between pin P4 and vminus signal. Write with ‘1’ to set bit.
MUX_FW_P5_VMINUS

Firmware control: 0=open, 1=close switch between pin P5 and vminus signal. Write with ‘1’ to set bit.
MUX_FW_P6_VMINUS

Firmware control: 0=open, 1=close switch between pin P6 and vminus signal. Write with ‘1’ to set bit.
MUX_FW_P7_VMINUS

Firmware control: 0=open, 1=close switch between pin P7 and vminus signal. Write with ‘1’ to set bit.
MUX_FW_VSSA_VMINUS

Firmware control: 0=open, 1=close switch between vssa_kelvin and vminus signal. Write with ‘1’ to set bit.
MUX_FW_TEMP_VPLUS

Firmware control: 0=open, 1=close switch between temperature sensor and vplus signal, also powers on the temperature sensor. Write with ‘1’ to set bit.
MUX_FW_AMUXBUSA_VPLUS

Firmware control: 0=open, 1=close switch between amuxbusa and vplus signal. Write with ‘1’ to set bit.
MUX_FW_AMUXBUSB_VPLUS

Firmware control: 0=open, 1=close switch between amuxbusb and vplus signal. Write with ‘1’ to set bit.
MUX_FW_AMUXBUSA_VMINUS

Firmware control: 0=open, 1=close switch between amuxbusa and vminus signal. Write with ‘1’ to set bit.
MUX_FW_AMUXBUSB_VMINUS

Firmware control: 0=open, 1=close switch between amuxbusb and vminus signal. Write with ‘1’ to set bit.
MUX_FW_SARBUS0_VPLUS

Firmware control: 0=open, 1=close switch between sarbus0 and vplus signal. Write with ‘1’ to set bit.
MUX_FW_SARBUS1_VPLUS

Firmware control: 0=open, 1=close switch between sarbus1 and vplus signal. Write with ‘1’ to set bit.
MUX_FW_SARBUS0_VMINUS

Firmware control: 0=open, 1=close switch between sarbus0 and vminus signal. Write with ‘1’ to set bit.
MUX_FW_SARBUS1_VMINUS

Firmware control: 0=open, 1=close switch between sarbus1 and vminus signal. Write with ‘1’ to set bit.
MUX_FW_P4_COREIO0

Firmware control: 0=open, 1=close switch between P4 and coreio0 signal. Write with ‘1’ to set bit.
MUX_FW_P5_COREIO1

Firmware control: 0=open, 1=close switch between P5 and coreio1 signal. Write with ‘1’ to set bit.
MUX_FW_P6_COREIO2

Firmware control: 0=open, 1=close switch between P6 and coreio2 signal. Write with ‘1’ to set bit.
MUX_FW_P7_COREIO3

Firmware control: 0=open, 1=close switch between P7 and coreio3 signal. Write with ‘1’ to set bit.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data